FIG. 1 is an explanatory diagram illustrating a configuration example of an amplifying circuit. The amplifying circuit includes an n-channel field-effect transistor (FET) 101 for amplifying an input signal supplied from a signal source 100. The input signal from the signal source 100 is first passed through a resistor R10 and then fed into a capacitor C10 where the DC component of the input signal is removed. The input signal whose DC component is thus removed, is then summed with a gate bias voltage, and the resulting signal is applied to the gate terminal of the FET 101. The gate bias voltage is supplied from a power supply line that supplies predetermined voltage Vg via a resistor R11; this power supply line is grounded via a capacitor C11.
The drain terminal of the FET 101 is coupled via an inductor L10 to a power supply line that supplies voltage Vd. This power supply line is grounded via a capacitor C12. The amplified signal obtained by amplifying the input signal through the FET 101 is output from its drain terminal and applied via a DC component removing capacitor C13 to a load 102.
The gate voltage biasing method of the FET 101 includes a class of operation intended for power conservation, which is described as class B operation, class C operation, etc., according to the magnitude of the voltage applied to the gate. The biasing method further includes a class of operation described as class AB operation in which bias current flows even during a period when there is no input signal in order to avoid signal waveform distortion that occurs near the pinch-off voltage, though this operation increases power consumption compared with the above two classes.
There is proposed an amplifier substantially free from crossover distortion, which combines the low distortion characteristic of a class AB amplifier with the low power consumption characteristic of a class B amplifier. The proposed amplifier has a signal expansion characteristic for the purpose of reducing noise at no-signal or low-signal levels.
There is also proposed a power amplifier for high-frequency applications that is low in distortion and that can be reduced in size, in which a bipolar transistor amplifies an input signal containing a plurality of frequency components, and a difference frequency signal that the transistor produces in relation to the input signal is detected by a collector choke inductor that constitutes a difference frequency signal detecting means. Then, based on the level of the detected difference frequency signal, a bias control circuit controls a base voltage source to vary the bias point of the transistor. In this way, when amplifying a large-amplitude signal that can produce a distortion from the transistor, the distortion is suppressed by operating the amplifier in class A having good linearity, and when amplifying a small-amplitude signal that does not produce a distortion from the transistor, the amplifier is operated close to class B to enhance power efficiency.
Related art is disclosed in Japanese Unexamined Patent Publication No. H06-21730 and Japanese Unexamined Patent Publication No. 2002-43855.